Simulation of the Synthetic Test Circuit of DC Switch Valve and Establishment of Its Physical Model

HVDC valve is the core component of the special/ultra-high voltage DC transmission project. It is mainly composed of thyristors and other auxiliary components. The safe and stable operation of the converter valve is inseparable from the development of the operational test technology. The converter valve operation test is mainly used to examine the operating capability of the sample valve under various steady state, transient and fault conditions. The traditional converter valve operation test adopts a direct back-to-back pulsation bridge test circuit. The test equivalency of the method is relatively high, but with the further development of UHVDC transmission, the flow capacity of the single-stage thyristor is greatly increased, making a direct test. The circuit's test capacity has also increased significantly. If you continue to use the direct test circuit for testing, you need to provide a huge test capacity of 100 MVA or more. The cost will be very high, and the design and manufacture of test equipment will be difficult. The direct test method is not suitable for the operation test of modern large-capacity converter valve.

Synthetic test loops came into being, which has become a widely used test method and a method recommended by the IEC standard. By controlling the trigger pulse of the test circuit, the method periodically applies a high voltage source and a large current source to the sample valve, so that the required capacity of a single power source is small, thereby reducing the overall test capacity. Synthetic test methods should be able to take into account the economics of testing and test equivalence.

Since the DC converter valve only withstands current when it is turned on, and only withstands voltage when it is turned off, the synthetic test circuit is composed of a high voltage loop and a large current loop for this feature. Two different power supplies are used and one is a large current. The source provides high current when the converter valve is conducting, and the other is a high voltage source that provides transient recovery voltage and power frequency recovery voltage when the converter valve is turned off.

The thyristor is an ideal device for simulation, and the thyristor during the test is not ideal. Its shutdown characteristics and spurious parameters will affect the test waveform; losses in the physical model circuit, such as the resistance of the reactor itself, the wire, are inevitable. The resistance and so on, while the simulation of the device is ideal; although the driver board is isolated, but the actual test, it can not completely eliminate the impact. In addition, the current waveform of the physical model agrees well with the simulation results. The waveforms are the same and the error is only 5.7%. The principle of the continuous operation load test and the control pulse timing have been introduced. The difficulty of control lies in the determination of the current introduction time point of the high voltage loop. The working principle of the test loop requires that the high current of the current loop be introduced to reduce the high current when the current loop is switched off.

Through the establishment of the physical model of the converter valve synthesis test circuit and the simulation study of the synthetic test circuit, the correctness of the synthetic test circuit design and the reliability of the simulation are verified. The parameters of the synthetic test circuit are adjustable, the test voltage and the test current are high, taking into account the economy and equivalence of the test, and the control difficulty is relatively small. Through appropriate parameter adjustment and triggering timing control, the synthetic test loop can run tests of different projects and provide correct voltage/current test waveforms.